Allwinner /D1H /SMHC[0] /SMHC_MINTSTS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SMHC_MINTSTS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (M_RE_INT)M_RE_INT 0 (M_CC_INT)M_CC_INT 0 (M_DTC_INT)M_DTC_INT 0 (M_DTR_INT)M_DTR_INT 0 (M_DRR_INT)M_DRR_INT 0 (M_RCE_INT)M_RCE_INT 0 (M_DCE_INT)M_DCE_INT 0 (M_RTO_BACK_INT)M_RTO_BACK_INT 0 (M_DTO_BDS_INT)M_DTO_BDS_INT 0 (M_DSTO_VSD_INT)M_DSTO_VSD_INT 0 (M_FU_FO_INT)M_FU_FO_INT 0 (M_CB_IW_INT)M_CB_IW_INT 0 (M_DSE_BC_INT)M_DSE_BC_INT 0 (M_ACD_INT)M_ACD_INT 0 (M_DEE_INT)M_DEE_INT 0 (M_SDIO_INT)M_SDIO_INT 0 (M_CARD_INSERT)M_CARD_INSERT 0 (M_CARD_REMOVAL_INT)M_CARD_REMOVAL_INT

Description

Masked Interrupt Status Register

Fields

M_RE_INT

Response Errors

M_CC_INT

Command Complete

M_DTC_INT

Data Transfer Complete

M_DTR_INT

Data Transmit Request

M_DRR_INT

Data Receive Request

M_RCE_INT

Response CRC Error

M_DCE_INT

Data CRC Error

M_RTO_BACK_INT

Response Timeout/Boot ACK Received

M_DTO_BDS_INT

Data Timeout/Boot Data Start

M_DSTO_VSD_INT

Data Starvation Timeout/V1.8 Switch Done

M_FU_FO_INT

FIFO Underrun/Overflow

M_CB_IW_INT

Command Busy and Illegal Write

M_DSE_BC_INT

Data Start Error/Busy Clear

M_ACD_INT

Auto Command Done

M_DEE_INT

Data End-bit Error

M_SDIO_INT

SDIO Interrupt

M_CARD_INSERT

Card Inserted

M_CARD_REMOVAL_INT

Card Removed

Links

()